Embodiments of the present invention relate to a semiconductor device, and more particularly to technology allowing detection of a defective state of a Through Silicon Via (TSV) at a wafer level.
In order to increase an integration degree of a semiconductor device, a three-dimensional (3D) semiconductor device has recently been developed, in which a plurality of chips is stacked and packaged in a single package. The 3D semiconductor device is formed by vertically stacking two or more chips, such that it can acquire a high integration degree in the same space.
Specifically, there has recently been used a Through Silicon Via (TSV) scheme for electrically interconnecting a plurality of chips by allowing a plurality of stacked chips to be penetrated through a silicon via. The semiconductor device using the TSV allows individual chips to be vertically penetrated such that the individual chips are interconnected, so that a package area may be reduced as compared with another semiconductor device configured to interconnect a plurality of chips through a line (or wire) located at an edge.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device.
Referring to FIG. 1, when using the TSV, a plurality of chips having the same structure is stacked so that a single semiconductor device can be configured.
The single semiconductor device may include one master chip for controlling overall operations of the semiconductor device, and a plurality of slave chips for storing data.
In accordance with the semiconductor device shown in FIG. 1, a first metal M1 is formed over a TSV, and a second metal M2 is formed over the first metal M1 through a metal contact.
A third metal M3 is formed over the second metal M2 through the metal contact.
The conventional semiconductor device forms a chip on a wafer, and performs a stacking process upon completion of a dicing process such that it forms a package.
However, the conventional semiconductor device verifies chip-to-chip TSV connection after completion of packaging, such that it is impossible to screen defective TSV connection on a wafer level.
In FIG. 1, the reference number (A) illustrates a defective interface between a TSV and a first metal M1 according to a defective TSV.
FIG. 2 illustrates the problems encountered in a TSV structure shown in FIG. 1.
In the TSV structure for use in a multi-chip package, a copper (Cu) material filled in a TSV is expanded by a subsequent heat process.
Accordingly, a crack occurs by expansion of the Cu material such that a defective interface in which a TSV is not connected to an upper metal pad, occurs as shown in (A).
If a defective part occurs in a TSV pad as shown in (A), a chip-to-chip defective connection occurs during chip stacking.
A defective TSV pad is detected when the wafer is tested such that a fabrication process must be extended to a subsequent package.
However, a defective TSV is not detected when the wafer is tested in a current TSV structure, and a failed TSV operation can be detected only after packaging.
Therefore, unnecessary costs encountered in packaging of a defective material are generated.
FIGS. 3a and 3b illustrate a defective metal line for use in the TSV structure shown in FIG. 1.
FIG. 3a is a plan view illustrating a second metal line M2 formed over a TSV.
Referring to FIG. 3a, a second metal line M2 is normally formed when a defective TSV does not occur.
On the other hand, FIG. 3b shows a defective interface encountered in a TSV.
Referring to FIG. 3b, a defective second metal line M2 formed over a TSV is unnecessarily connected to a contiguous metal line as shown in (B).
The TSV structure is required for high-speed and high-capacity DRAM operations.
A mid-level structure configured not to consume high costs without great change of an inline fabrication as in a TSV can check its own connectivity after completion of such stacking.
Therefore, when a defective TSV connection occurs in the wafer process, it is difficult for the conventional semiconductor device to screen the defective TSV connection such that unnecessary costs are consumed when packaging of a defective chip.